Voltage multipliers to "pump" a voltage from a low source to a high source are well known in the art. Typically, they are used in non-volatile memory arrays in which the high voltage is required to program or erase the non-volatile memory cells. The supplied voltage is the "low" voltage and the "high" voltage is used to program or erase the memory cells. As supplied voltages have decreased due to integrated circuits being used in applications using only battery supplies, the low voltage has decreased. In the prior art, in order to effectively "pump" the low voltage to the high voltage, the voltage multipliers have used MOS transistors that have low initial threshold voltage and body effect so that the voltage drop across the MOS diode is minimized. Some prior art designs have used multiple-phase clock signals to boost the gate voltage of the MOS diode to compensate for the threshold drop and to improve the pumping efficiency.
FIG. 1 shows the design of a prior art single phase clock voltage multiplier circuit. Each pump stage is comprised of two MOS transistors, e.g. M1 and M2 for the first stage. Each transistor is connected in a diode configuration. Capacitors C1 and C2 supply the clock signals, CLK and CLK respectively, to M1 and M2, respectively. In such design the output voltage V.sub.out is determined by the following equation, assuming no current load is required from the output node: EQU V.sub.out =(V.sub.CC -V.sub.th)+N(V.sub.CLK C/(C+C.sub.s)-V.sub.th)(1)
where
(V.sub.CC -V.sub.th) is the voltage at the input to the first stage of the voltage multiplier after the voltage has passed through the transistor MVcc; PA1 V.sub.th is the threshold voltage of each transistor M.sub.(2n-1) and M.sub.(2n) in the multiplier; PA1 C is the capacitance of the coupling capacitor C.sub.(2n-1), and C.sub.(2n) in the nth stage of the multiplier, with C.sub.(2n-1) =C.sub.(2n) ; PA1 C.sub.s is the parasitic capacitance at the drain node of each transistor M.sub.(2n-1) and M.sub.(2n) in the multiplier; PA1 f is the frequency of the clock signal; PA1 V.sub.CLK is the voltage of the clock signal; and PA1 N is the total number of stages of the multiplier.
Typically, C/(C+C.sub.s) is.about.85% and V.sub.th can be from approximately 1 Volt to 2.5 Volt or higher depending on the degree of the body effect of the transistor which varies from process to process. V.sub.CLK typically is the same as V.sub.CC, When V.sub.CC is less than 3 V, the term V.sub.CLK C/(C+C.sub.s) is very close to the V.sub.th. This will severely degrade the pumping efficiency of the multiplier.
Thus, the prior art tried to eliminate V.sub.th or its effect to obtain a larger gain, e.g. to get higher V.sub.CLK on the gate of the transistors M, or to use multi-phase clock signals. See for example, U.S. Pat. No. 5,301,097; 5,422,586; 5,196,996; "On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique" by John F. Dickson, IEEE Journal of Solid-State Circuits, Vol SC-11, No. 3, June 1974; and A 5-V-Only Operation 0.6-um Flash EEPROM with Row Decoder Scheme in Triple-Well Structure" by Umezawa et. al, IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, November, 1992.